Short delay methods for the VLSI design of Viterbi decoder

Author

Jun, Yang ; Yang, Zhang Er

Author_Institution

Sch. of Electron. Sci. & Eng., Nat. Univ. of Defence Technol., Hunan, China

fYear

2002

fDate

17-19 Aug. 2002

Firstpage

237

Lastpage

240

Abstract

For the purpose of shortening the decoding delay, two VLSI design approaches for the SMU are concurrently studied in this paper. The hybrid approach of trace-back (TB) and trace-forward (TF) in addition to the optimization of the storage method makes the decoding delay greatly reduced. Then we provide a new hybrid approach of register exchange (RE) and TF which has more attractions than the traditional RE in the advantage of its simplification of the corresponding connection scheme.

Keywords

VLSI; Viterbi decoding; delays; digital signal processing chips; high-speed integrated circuits; integrated circuit design; 28 Mbit/s; 38 MHz; SMU; VLSI design approaches; Viterbi decoder; decoding delay reduction; hybrid approach; register exchange; short delay methods; storage method optimization; trace-back; trace-forward; Convolutional codes; Decoding; Delay effects; Design engineering; Iron; Joining processes; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology, 2002. Proceedings. ICMMT 2002. 2002 3rd International Conference on

Print_ISBN

0-7803-7486-X

Type

conf

DOI

10.1109/ICMMT.2002.1187679

Filename

1187679

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3304693