Title :
A sub-half micron partially gate-to-drain overlapped MOSFET optimized for high performance and reliability
Author :
Chen, I.C. ; Chapman, R.A. ; Teng, C.W.
Author_Institution :
Texas Instruments, Dallas, TX, USA
Abstract :
A partially gate-to-drain overlapped n-channel MOSFET using poly spacers was studied and compared to a fully overlapped and a conventional oxide spacer device in terms of performance and reliability. It is shown that, for a 500-AA partial overlap (flanked with 700-AA oxide spacer) device, the gate-to-drain overlap capacitance and simulated inverter delay are only 12% and 8%, respectively, higher than those of a conventional oxide spacer device. At a given performance level, the partial overlap device has two orders of magnitude longer DC hot-carrier lifetime than that of an oxide spacer device. The reason the overlapped device has high resistance to the hot-carrier stressing is the adverse oxide field at V/sub G/>
Keywords :
hot carriers; insulated gate field effect transistors; reliability; 0.5 micron; 200 to 300 A; 700 A; DC hot-carrier lifetime; gate-to-drain overlap capacitance; gate-to-drain overlap distance; hot-carrier stressing; inverter delay; partial overlap device; partially gate-to-drain overlapped MOSFET; performance; poly spacers; reliability; sub-half micron MOSFET; Capacitance; Degradation; Electron traps; Hot carriers; Implants; Inverters; MOSFET circuits; Power supplies; SPICE; Voltage;
Conference_Titel :
Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0243-5
DOI :
10.1109/IEDM.1991.235411
