Advantages of CVD stacked gate oxide for robust 0.5 mu m transistors

Several attractive device characteristics achieved by implementing thermal/CVD (chemical vapor deposited) stacked gate oxide have been observed. A CVD stacked gate oxide process is shown to dramatically reduce process-induced device degradation problems such as threshold voltage scatter as compared with conventional thermal gate oxide. A tighter channel length distribution and wider channel width can be provided by the stacked gate dielectric. The low voltage failures on SRAM defect arrays and the mid-gap interface state density are both about 4* smaller for stacked dielectric than for the conventional thermal oxide. These attractive advantages make a CVD stacked gate oxide a promising candidate for submicron technology.<>