The Mixed-Signal Design of PLL with CMOS Technology

State of art phase locked loop (PLL) design methodologies and techniques are always of many mixed-signal circuit designers´ interests. In this paper, a fully differential PLL having good common-mode noise rejection (low phase noise) has been designed and demonstrated using TSMC 0.25mum CMOS technology. The design and demonstration included a dead zone eliminating phase frequency detector (PFD) with complimentary signals, a differential charge pump/loop filter (CP-LPF) with common mode feedback, a differential voltage controlled oscillator (VCO) with two stage only differential hysteresis delay cell and a divider. Using the full-custom design flow, each individual building block, like PFD, CP/LPF , VCO and divider has been designed, simulated, extracted (DRC and LVS) and verified (transistor level bottom up verification), then followed by the top level PLL simulation, extraction and verification.