Design methodology and practice of VLSI functional test synthesis

Author

Hudec, Ján

Author_Institution

Dept. of Comput. Sci. & Eng., Slovak Univ. of Technol., Bratislava, Slovakia

fYear

2001

fDate

19-22 June 2001

Firstpage

461

Abstract

The paper presents a methodology overview for test synthesis of VLSI and ASIC systems using an automated process of VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction mixes is discussed.

Keywords

VLSI; application specific integrated circuits; automatic test software; hardware description languages; AFTG; ASIC systems; Automatic Functional Test Generator; VHDL synthesis; VLSI functional test synthesis; automated process; design methodology; instruction mixes; methodology overview; test efficiency; Application specific integrated circuits; Automatic testing; Circuit testing; Design automation; Design methodology; Electronic equipment testing; Integrated circuit synthesis; Production; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology Interfaces, 2001. ITI 2001. Proceedings of the 23rd International Conference on

ISSN

1330-1012

Print_ISBN

953-96769-3-2

Type

conf

DOI

10.1109/ITI.2001.938056

Filename

938056

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3305274