Constraint transformation for IC physical design

Author

Malavasi, Enrico ; Charbon, Edoardo

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

1998

fDate

35953

Firstpage

46

Lastpage

49

Abstract

In a top-down design methodology, design tasks are divided into simpler sub-tasks across levels of hierarchy and abstraction as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into sub-task requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach for industrial-strength applications

Keywords

analogue integrated circuits; integrated circuit design; integrated circuit modelling; IC physical design; analog circuit applications; constraint transformation; design abstraction; design hierarchy; design sub-tasks; design task division; divide-and-conquer technique; industrial-strength applications; nondeterministic process parameter variation; performance characteristics; performance mismatches; performance parasitics; performance specifications; top-down design methodology; Analog circuits; Degradation; Delay; Design methodology; Electrical resistance measurement; Fabrication; Process design; Stochastic processes; Stress; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Metrology, 1998. 3rd International Workshop on

Conference_Location

Honolulu, HI

Print_ISBN

0-7803-4338-7

Type

conf

DOI

10.1109/IWSTM.1998.729767

Filename

729767