Patterning of Sub-0.18/spl mu/m Logic Gates with Phase-Edge PSM

Author

Cha, D. ; Kye, J. ; Seong, N. ; Kang, H. ; Cho, H. ; Moon, J.

Author_Institution

Samsung Electronics Co., Ltd.

fYear

1998

fDate

13-16 July 1998

Firstpage

106

Lastpage

108

Keywords

Chromium; Circuit simulation; Etching; Lenses; Logic circuits; Logic design; Logic gates; Random access memory; Size control; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocesses and Nanotechnology Conference, 1998 International

Conference_Location

Kyoungju, South Korea

Print_ISBN

4-930813-83-2

Type

DOI

10.1109/IMNC.1998.729994

Filename

729994

Link To Document