VLSI design methodologies for application specific binary sensors

As application specific sensors will only have small to medium fabrication runs, non-recurrent design time costs are a dominant factor in the production of CMOS custom VLSI. The ability to reduce these costs and partly deskill the process of full custom VLSI design is essential to the economic viability of such sensors. Any methodology implemented to simplify the design process must be flexible enough to enable the development of sensors with any particular resolution, combined simple processing functions and on-chip memory. The case studies show that the proposed methodology enables application specific binary sensors of differing array sizes and processing to be designed and laid out quickly and simply, using a library of cells. The generic bit-sliced library cells and full-custom logic are slower to produce initially, but their potential for repeated use in many designs makes this penalty worthwhile. Circuits for bit-sliced processing need to contain some redundant logic and buffering to make the cells as generic as possible, and so some functions are less efficient to implement in bit-sliced form. However, it has been discovered that this is compensated by an increase in packing density of bit-sliced cells of typically 16-21%, compared to auto-routed logic