Principle of CMOS circuit power-delay optimization with transistor sizing

Transistor sizing is used for optimizing the power-delay product rather than only delay of a CMOS circuit in this paper. The objective is to satisfy a given delay with the least power. Optimum sizes are analyzed for transistors in a transistor chain, a gate and a gate chain and discussions are given to the case of a complete CMOS circuit. The principle is useful not only in “manual” transistor sizing but also in making CAD tools for power-delay optimization under a given delay goal