Impact of intrinsic gate-drain capacitance on noise performance of CMOS LNA

The impact of the intrinsic gate-drain capacitance on the noise performance of an inductively degenerated LNA is modeled and analyzed in this paper. It is shown that neglecting the gate-drain capacitance leads to an overestimation of the optimum device width, which degrades the noise performance of an LNA. Revised noise figure optimization technique is proposed to compensate for this degradation. All this work will be very instructive to the design of high-performance LNAs.