Title :
Fully CMOS compatible gate-shifted LDD-NMOS
Author :
Santos, P. ; Casimiro, A.P. ; Simas, M. I Castro ; Lança, M.
Author_Institution :
Inst. de Telecomunicacoes, Inst. Superior Tecnico, Lisbon, Portugal
Abstract :
This work investigates, through extensive two-dimensional device simulation and experiments on prototypes, the prospects of integrating high-voltage blocking capability NMOS devices into a standard submicron, low cost, CMOS technology with no extra processing steps. With this new device, GSLDD-NMOS, breakdown voltages in the range of 50 volt and specific ON-resistances in the range of 3 m/spl Omega/.cm/sup 2/ were attained. Its performance is compared with other high performant devices, fabricated in more sophisticated technologies. The proposed device is, therefore, highly suitable for the implementation of very low cost smart power circuits.
Keywords :
CMOS integrated circuits; power MOSFET; power integrated circuits; semiconductor device breakdown; 50 V; CMOS compatible gate-shifted LDD-NMOS; breakdown voltages; gate shifted lightly doped drain NMOS; high-voltage blocking capability NMOS devices; smart power IC; smart power circuits; specific ON-resistances; submicron CMOS technology; two-dimensional device simulation; BiCMOS integrated circuits; CMOS process; CMOS technology; Circuit simulation; Costs; Foundries; MOS devices; Telecommunications; Virtual prototyping; Voltage;
Conference_Titel :
Industry Applications Conference, 1998. Thirty-Third IAS Annual Meeting. The 1998 IEEE
Conference_Location :
St. Louis, MO, USA
Print_ISBN :
0-7803-4943-1
DOI :
10.1109/IAS.1998.730287
