• DocumentCode
    330844
  • Title

    The reliability improvement on self-aligned contact CMOS by optimizing poly etching

  • Author

    Chang, Chai-Der ; Chu, Cheng-Yu ; Lin, Dean-E

  • Author_Institution
    Taiwan Semicond. Manuf. Co., Taiwan
  • fYear
    1998
  • fDate
    19-21 Oct 1998
  • Firstpage
    136
  • Lastpage
    138
  • Abstract
    The advanced 2 μm self-aligned contact CMOS IC with ONOP (oxide-nitride-oxide-polysilicon) structure has similar device dimensions to conventional 1 μm CMOS ICs. A special isolation method of sidewall oxidation with a nitride cap layer is used to isolate the poly and metal. The minimum design rule for contact-to-poly distance is zero, which allows the designer to shrink this CMOS device dimension to near the 1 μm conventional CMOS dimensions, even though the 2 μm process has been used. However, the poly profile must be well controlled in this process and must remain sharp after poly etching, or the top corner of the isolated nitride cap will be etched, resulting in nitride cracking along the top corner of the poly sidewall. A two-step poly profile is shown to be the major cause of isolated nitride cap cracking. In the research, an in-situ poly etch for the ONOP structure was developed which can obtain a sharp poly profile. According to our TSUPREM4 simulation and experimental data, the poly can not be exposed outside the ONO structure over a certain range, or isolated nitride cap cracking will occur
  • Keywords
    CMOS integrated circuits; cracks; etching; integrated circuit reliability; integrated circuit testing; isolation technology; nitridation; oxidation; semiconductor process modelling; 1 micron; 2 micron; CMOS ICs; CMOS device dimension; ONOP structure; SiO2-Si3N4-SiO2-Si; TSUPREM4 simulation; contact-to-poly distance; design rule; device dimensions; in-situ poly etch; isolated nitride cap; isolated nitride cap cracking; isolation method; metal isolation; nitride cap layer; nitride cracking; oxide-nitride-oxide-polysilicon structure; poly etch exposure; poly etching; poly etching optimization; poly isolation; poly profile control; poly sidewall; reliability; self-aligned contact CMOS; self-aligned contact CMOS IC; sharp poly profile; sidewall oxidation; two-step poly profile; Anisotropic magnetoresistance; Biographies; CMOS integrated circuits; CMOS process; Chemistry; Contacts; Dry etching; Electrical engineering; Etching; Oxidation; Polymers; Process control; Semiconductor device manufacture; Wet etching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 1998. Twenty-Third IEEE/CPMT
  • Conference_Location
    Austin, TX
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-4523-1
  • Type

    conf

  • DOI
    10.1109/IEMT.1998.731067
  • Filename
    731067