Title :
Compaction of IDDQ test sequence using reassignment method
Author :
Maeda, Toshiyuki ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we propose an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.
Keywords :
CMOS logic circuits; automatic test pattern generation; combinational circuits; electric current measurement; fault simulation; logic testing; sequential circuits; CMOS circuits; IDDQ testing; combinational circuits; current measurement; fault simulation; internal short faults; less computation time; reassignment method; sequential circuit gates; short faults detection; short sequences; signal values reassignment; test sequence compaction; weighted random vectors; Circuit faults; Circuit testing; Compaction; Current measurement; Electrical fault detection; Fault detection; Logic testing; Sequential analysis; Sequential circuits; Time measurement;
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
DOI :
10.1109/ETW.1999.804210
