DocumentCode
3309287
Title
Wafer-scale BCB resist-processing technologies for high density integration and electronic packaging
Author
Pelzer, Rainer ; Dragoi, Viorel ; Swinnen, Bart ; Soussan, Philippe ; Matthias, Thorsten
Author_Institution
EV Group, Schaerding, Austria
fYear
2005
fDate
11-14 Dec. 2005
Firstpage
187
Lastpage
191
Abstract
IC performance is drastically limited by line-to-line capacity coupling and RC interconnect delay times resulted from the continuous increase in integration densities with 0.10μm line and space width approaches, as well from increased signal frequencies. The new achievements in terms of circuit lines shrinkage emphasize the need for the introduction of Cu and low-k dielectric materials The main properties of the dielectric materials required for a large field of versatile applications/designs can be summarized in: isotropic dielectric constants (2.65-2.5@ 1MHz-10GHz), good thermal stability, low CTE and a good adhesion to different substrates. Commercially available benzocyclobutene (BCB)-based polymer dielectrics, like cyclotone from Dow Chemical Company can fulfil these demands. The new materials not only opened new application areas, but also penetrated well established technologies. The extensive field of BCB-based applications ranges from interlayer dielectric applications - chip stacking by vertical 3D interconnections, to pad redistribution layers and device encapsulation. These technologies realized in vertical interconnection and wafer-level packaging (WLP), are viable solutions for increasing electronic device functional density and reducing total packaging costs. This paper reports on different BCB applications for wafer-to-wafer adhesive bonding for 3D integration, sprays coating for encapsulation and photo-structuring using a proximity mask aligner for pad redistribution and integrated passives.
Keywords
dielectric materials; electronics packaging; encapsulation; integrated circuit interconnections; masks; wafer-scale integration; benzocyclobutene based polymer dielectrics; chip stacking; device encapsulation; electronic packaging; high density integration; integrated passives; interlayer dielectric applications; pad redistribution layers; proximity mask aligner; vertical 3D interconnections; wafer-level packaging; wafer-scale BCB resist-processing; wafer-to-wafer adhesive bonding; Chemical technology; Coupling circuits; Delay; Dielectric materials; Dielectric substrates; Electronics packaging; Encapsulation; Integrated circuit interconnections; Space technology; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Materials and Packaging, 2005. EMAP 2005. International Symposium on
Print_ISBN
1-4244-0107-0
Type
conf
DOI
10.1109/EMAP.2005.1598259
Filename
1598259
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