Comprehensive defect analysis and defect coverage of CMOS circuits

Author

Al-Khalili, D. ; Adham, S. ; Rozon, C. ; Hossain, M. ; Racz, D.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1998

fDate

2-4 Nov 1998

Firstpage

84

Lastpage

92

Abstract

In this paper we present a methodology to perform defect analysis of digital CMOS circuits using comprehensive transistor macro defect models. These models are based on eighteen defects, hard and soft, for each MOS transistor. Defects are activated individually and circuits are exhaustively simulated to determine the responses, which are then compared with that of gold circuits. Both defect and fault coverages are determined including statistics to determine the effectiveness of a testing method. Results on combined testing and implications on incremental fault coverages are presented

Keywords

CMOS integrated circuits; circuit simulation; fault diagnosis; integrated circuit modelling; integrated circuit testing; CMOS circuits; defect analysis; defect coverage; exhaustive circuit simulation; incremental fault coverages; testing method; transistor macro defect models; Circuit faults; Circuit simulation; Circuit testing; Diodes; MOSFETs; Military communication; Performance analysis; Resistors; Semiconductor device manufacture; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on

Conference_Location

Austin, TX

ISSN

1550-5774

Print_ISBN

0-8186-8832-7

Type

conf

DOI

10.1109/DFTVS.1998.732154

Filename

732154