Title :
High-level path activation technique to speed up sequential circuit test generation
Author :
Raik, Jaan ; Ubar, Raimund
Author_Institution :
Tallinn Tech. Univ., Estonia
Abstract :
In current paper, a novel high-level symbolic path activation technique for sequential circuit test generation is proposed. The technique has been implemented as a part of a hierarchical ATPG tool which utilizes internal representation of multi-level (register-transfer and structural levels) decision diagram models. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time.
Keywords :
automatic test pattern generation; constraint handling; decision diagrams; fault diagnosis; hierarchical systems; logic testing; sequential circuits; decision diagram models; fault coverages; hierarchical ATPG tool; high-level path activation; high-level symbolic path activatio; multi-level decision diagram models; register-transfer levels; sequential circuit test generation; structural levels; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Joining processes; Sequential analysis; Sequential circuits; Software testing; Test pattern generators;
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
DOI :
10.1109/ETW.1999.804289
