Closed Form Bandwidth Expression for Distributed On-chip RLCG Interconnects

With the increasing levels of on-chip integration, more functional units are integrated onto a single die, the logic delays decrease due to faster transistors. At the same time, local interconnect delays similarly improve because the physical size of circuit blocks decrease, and the local interconnect spans shorter distances. During the interconnect design process, multiple design criteria are considered, such as delay, power, bandwidth, and noise. Performance of any high speed VLSI circuit depends on the bandwidth as it decreases with increase in the length of interconnects. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. In case of very high frequency as in Gigascale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RLC model. Unfortunately, this model has many limitations which can lead to inaccurate simulations if not modeled correctly. In this paper our main focus is to estimate the bandwidth of the distributed RLCG interconnects for high speed devices. A closed form solution for bandwidth is obtained by incorporating initial conditions approach for distributed RLCG interconnects for high speed devices.