Design and Analysis of VCO in PLL System

Author

Xiu-long, Wu ; Jun-ning, Chen ; Jian, Meng

Author_Institution

Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing

Volume

2

fYear

2009

fDate

25-26 April 2009

Firstpage

7

Lastpage

9

Abstract

A wide-bandwidth low-noise VCO used in PLL system was investigated, including a harmonic filtering resistor and source damping resistors to reduce the phase noise and power dissipation. The back-to-back varactor topology is identified as a suitable solution to linearize the tank capacitance. The amplitude to phase noise conversion is greatly attenuated. The circuit was simulated using 0.35 mum CMOS technology in Mentor Graphics Eldo-RF environment, the simulation results show that the phase noise of the oscillator can reach -119.5 dBc/Hz@1 MHz, the power dissipation is 3.0 mw at 2.4 GHz.

Keywords

CMOS integrated circuits; network topology; phase locked loops; resistors; varactors; voltage-controlled oscillators; CMOS technology; Mentor Graphics Eldo-RF environment; PLL system; VCO; frequency 2.4 GHz; harmonic Altering resistor; phase noise reduction; power 3 mW; power dissipation reduction; size 0.35 mum; source damping resistors; varactor topology; voltage controlled oscillators; CMOS technology; Circuit simulation; Filtering; Phase locked loops; Phase noise; Power dissipation; Power harmonic filters; Power system harmonics; Resistors; Voltage-controlled oscillators; PLL; Phase noise; VCO;

fLanguage

English

Publisher

ieee

Conference_Titel

Networks Security, Wireless Communications and Trusted Computing, 2009. NSWCTC '09. International Conference on

Conference_Location

Wuhan, Hubei

Print_ISBN

978-1-4244-4223-2

Type

conf

DOI

10.1109/NSWCTC.2009.392

Filename

4908392