Highly Efficient True Random Number Generator in FPGA Devices Using Phase-Locked Loops

This paper presents a new type of True Random Number Generator (TRNG) based on jitter and metastability implemented in the latest family of Xilinx FPGA devices. The source of randomness is the Phase-Locked Loop (PLL) that is present on such devices, which exhibits jitter due to one of the analog component in it. For extracting the random bits the design uses the same clock as the PLL´s input clock. The quality of the TRNG is given by the entropy source used, the single-chip implementation, and the high throughput (of the order of several megabits per second) obtained. It is confirmed by the fact that all the classical test batteries (NIST, DIEHARD, Test U01 and ENT) yielded very good results when ran on the generated random bits stream.