Parallel-and-vector implementation of the event-driven logic simulation algorithm on the Cray Y-MP supercomputer

The authors propose logic simulation techniques using parallel and vector machines to reduce the simulation time of large digital circuits. Three algorithms for logic simulation have been developed and implemented on the Cray Y-MP supercomputer, a general-purpose shared-memory parallel machine with vector processors. The first is a vector version of the event-driven algorithm that achieves a speedup of 13.6 on a single Cray Y-MP processor. The second is a parallel version of the event-driven algorithm that achieves a speedup of 6.3 with eight processors. The third is a complete parallel and vector version of the event-driven algorithm that achieves a speedup of 52 on the Cray Y-MP with eight processors. The proposed techniques are very general so that they can be implemented on other computers without major modifications. Comparisons between the three algorithms and commercial logic simulators are included