The design of the M3S: a multiported shared-memory multiprocessor

The design of M3S, an academic shared-memory multiprocessor, is described. The memory is divided into modules. Each processor (through its cache) has an access to each memory module only through a high-throughput private serial link. Each memory module has several serial ports that are connected, in parallel, to the memory. The data coherency is maintained by a hardware directory-based scheme. The interconnection network has no bottleneck since each processor has its private path to each memory module. The high bit rate of the serial links is the most important technical problem for the design of this prototype. Synchronous solutions have been chosen in the prototype because of their greater simplicity. The data rate on the serial links is 800 Mb/s. Choices made in order to realize this project with one memory module and sixteen processor modules are explained