Deterministic BIST with partial scan

An efficiency deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flip-flops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flip-flops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.