Convolution operation implemented in FPGA structures for real-time image processing

Addition is an essential operation for convolution (or FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates the search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of addition inputs have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: multiplierless multiplication, look-up table based multiplication, distributed arithmetic. Furthermore, different optimisation techniques, exhausted search and simulated annealing, have been implemented. Otherwise, exhausted search should be employed for the number of the addition inputs n⩽8 or simulated annealing for n>8. Employing simulated annealing gives about 10-20% area reduction in comparison to the greedy algorithm. This paper is a part of the research on the AuToCon-automated tool for generating convolution in FPGAs