On maximizing the coverage of catastrophic and parametric faults

Author

Brosa, Anna M. ; Figueras, Joan

Author_Institution

Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain

fYear

1999

fDate

25-28 May 1999

Firstpage

123

Lastpage

128

Abstract

The purpose of this paper is to analyze an optimization method to improve the testability of structural and parametric faults in analog circuits. The approach consists of finding an optimum sub-set of tests which maximizes the fault coverage with minimum cost. The method is based on covering a discrete set of intervals by taking advantage of strategies effectively used in digital synthesis. A simple application example is given to illustrate the proposal by studying the fault coverage obtained using different test sets on the ITC´97 benchmark op-amp.

Keywords

analogue circuits; design for testability; fault simulation; integrated circuit economics; operational amplifiers; optimisation; CMOS; ITC´97 benchmark op-amp; analog circuits; catastrophic faults; digital synthesis; fault coverage; floating gate; minimum cost; optimization; optimum sub-set of tests; parametric faults; resistive bridges; structural faults; testability; Analog circuits; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Cost function; Fault detection; Operational amplifiers; Optimization methods; Proposals;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Workshop 1999. Proceedings

Conference_Location

Constance, Germany

Print_ISBN

0-7695-0390-X

Type

conf

DOI

10.1109/ETW.1999.804430

Filename

804430