Design and Realization of an Optimized Memory Access Scheduler

Memory Wall is a bottleneck of enhancing the performance of computer system, and appearance of multiprocessors (CMPs) makes it more. How to reduce Memory Access Latency is a critical issue we have to deal with. Memory controller is difficult to optimize, the controller needs to obey all DRAM timing constraints to provide correct functionality. State-of -the-art DDR2 SDRAM chips often have a large number of timing constraints that must be obeyed when scheduling commands, for instance, over 50 timing constrains. We have made deep research on optimized memory access scheduling. In order to efficiently utilize the bandwidth and reduce the latency, Memory Access Scheduling optimization adapts the characters of DRAM to reschedule the memory access. By studying effective data bar which is generated by Genetic Algorithm, we mine four rules. So we just use these four rules to schedule in Memory Access Controller. The results of experiment show that compared with FR-FCFS (first-ready first-come first-serve) scheduling strategy, the rule based algorithm improves the performance of scheduling and the ideal speedup is near 1.5 times. The best speedup of the test of spec2000 is 1.467, and the worst speedup is 1.078.