DocumentCode
3312702
Title
VectorSTM: Software Transactional Memory without Atomic Instructions
Author
Peng, Lin ; Xie, Lun-guo ; Zhang, Xiao-qiang ; Xie, Xin-yan
Author_Institution
Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
Volume
2
fYear
2010
fDate
28-31 May 2010
Firstpage
278
Lastpage
282
Abstract
Transactional Memory(TM) is a promising way to coordinate concurrent threads in multi-core processors. Software transactional memory (STM) can run on conventional processors without additional hardware support. In this paper we propose VectorSTM which reduces the cost of centralized concurrency control. VectorSTM employs distributed vector timestamps instead of a single global timestamp to track the progress of transactions. Conflict detecting and transaction committing are done by polling thread local bloom filter queues which are indexed by the vector timestamps. Without employing any atomic instructions, VectorSTM reduces synchronization cost on the global timestamp variable and provides more concurrency. VectorSTM provides privatization safety which is critical to software transactional memory safety and avoids live lock and starvation by effective contention manager. We evaluate VectorSTM with STAMP benchmarks and the results show that the design offer superior performance or stronger semantics than TL2 and RingSTM algorithm. On particular tests VectorSTM outperforms TL2 and RingSTM 27% and 41% respectively with 8 threads running.
Keywords
concurrency control; multi-threading; multiprocessing systems; transaction processing; RingSTM algorithm; STAMP benchmark; VectorSTM; atomic instruction; centralized concurrency control; contention manager; coordinate concurrent threads; distributed vector timestamp; global timestamp variable; multicore processor; polling thread local bloom filter queues; software transactional memory; software transactional memory safety; synchronization cost; transactional memory; Concurrency control; Concurrent computing; Memory management; Multicore processing; Software safety; atomic instructions; multi-core processors; software transactional memory; vector timestamp;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Science and Optimization (CSO), 2010 Third International Joint Conference on
Conference_Location
Huangshan
Print_ISBN
978-1-4244-6812-6
Electronic_ISBN
978-1-4244-6813-3
Type
conf
DOI
10.1109/CSO.2010.145
Filename
5533020
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