A defect and fault tolerant interconnection network strategy for WASP devices

The paper presents an investigation on interconnect defect occurrences observed on a WASP (i.e. WSI Associative String Processor) device, the WASP 2B, as part of an ongoing WSI interconnect experimental study that started on a sister device, the WASP 2A. Thus, after a brief overview of the WASP 2B device and the analysis of observed defect data on its interconnect, this paper examines: (i) the implications of these experimental studies and (ii) strategies necessary for the implementation of a defect and fault tolerant interconnection network for future WASP devices (i.e. WASP 3, 4, and 5), in the light of the experiences gained