Augmenting scan path SRLs with an XOR network to enhance delay fault testing

Author

Zhang, Zaifu ; McLeod, Robert D. ; Pedrycz, Witold

Author_Institution

Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

fYear

1994

fDate

17-19 Oct 1994

Firstpage

55

Lastpage

63

Abstract

In this paper, we present a technique to enhance transition delay and stuck-open fault testing in an LSSD environment. To reduce shift dependency in the scan path, thereby improving transition quality, a re-arrangement heuristic combined with a one level XOR network is proposed. The method is hierarchical, combining a simple re-arrangement, heuristic driven local reconfiguration, and finally a circuit modification to improve delay fault testing

Keywords

shift registers; DFT; LSSD environment; VLSI; XOR network; circuit modification; combinational circuits; delay fault testing; heuristic driven local reconfiguration; re-arrangement heuristic; scan path SRLs; shift dependency; shift register latch; stuck-open fault testing; transition delay; Built-in self-test; Circuit faults; Circuit testing; Delay effects; Design for testability; Electrical fault detection; Fault detection; Integrated circuit testing; Propagation delay; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630014

Filename

630014