The Influence of NBL Layout and LOCOS Space on Component ESD and System Level ESD for HV-LDMOS

Author

Lee, Jian Hsing ; Chen, S.H. ; Tsai, Y.T. ; Lee, D.B. ; Chen, F.H. ; Liu, W.C. ; Chung, C.M. ; Hsu, S.L. ; Shih, J.R. ; Liang, Alan Y. ; Wu, Kenneth

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu

fYear

2007

fDate

27-31 May 2007

Firstpage

173

Lastpage

176

Abstract

This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current passage from the surface channel region to the bulk NBL during an ESD zapping, thus, avoiding localized highly damaging ESD current flow in the channel region.

Keywords

electrostatic discharge; integrated circuit layout; semiconductor device breakdown; semiconductor device reliability; semiconductor device testing; HV-LDMOS; LOCOS space; N-type buried layer layout; component ESD; lateral DMOS device; surface channel region; system level ESD; trigger voltage; Application specific integrated circuits; Displays; Driver circuits; Electrostatic discharge; Failure analysis; IEC standards; Space technology; Switches; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on

Conference_Location

Jeju Island

Print_ISBN

1-4244-1095-9

Electronic_ISBN

1-4244-1096-7

Type

conf

DOI

10.1109/ISPSD.2007.4294960

Filename

4294960