• DocumentCode
    3312996
  • Title

    On the testability of CMOS feedback amplifiers

  • Author

    Bishop, A.J. ; Ivanov, A.

  • Author_Institution
    Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
  • fYear
    1994
  • fDate
    17-19 Oct 1994
  • Firstpage
    65
  • Lastpage
    73
  • Abstract
    This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to simulate the faulty response of the opamp circuits. Our method relies on repeated Monte Carlo fault simulations to examine differences in a circuit´s response for each possible fault condition. A sine wave is used for the test stimulus in each case. Four closed loop configurations are considered for the study: integrator, differentiator, inverting amplifier, and comparator. We tally the percentage of stuck-at, short, and open faults that are detectable with the feedback applied to demonstrate that the four feedback network configurations have little effect on the catastrophic fault coverage, as compared with similar tests performed for an open-loop configuration
  • Keywords
    integrated circuit testing; CMOS feedback amplifiers; Monte Carlo fault simulations; catastrophic faults; closed loop configurations; comparator; differentiator; fault condition; faulty response; integrator; inverting amplifier; network configurations; open faults; operational amplifier; parameter variation fault models; short faults; sine wave; stuck-at faults; test stimulus; testability; wafer probe; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Feedback amplifiers; Monte Carlo methods; Operational amplifiers; Probes; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-6307-3
  • Type

    conf

  • DOI
    10.1109/DFTVS.1994.630015
  • Filename
    630015