Title :
Superjunction Power LDMOS on Partial SOI Platform
Author :
Chen, Yu ; Buddharaju, Kavitha D. ; Liang, Yung C. ; Samudra, Ganesh S. ; Feng, Han Hua
Author_Institution :
Nat. Univ. of Singapore, Singapore
Abstract :
Superjunction power LDMOS device implemented on the bulk Si substrate suffers from the substrate-assisted depletion (SAD) effect, which causes the charge imbalance, and thus limits the device performance. A new SJ-LDMOS structure integrated on the partial SOI (PSOI) platform is proposed in this paper, which eliminates the SAD completely and enables the making of SJ-LDMOS on bulk silicon substrate without sacrificing its electrical and thermal performance. The PSOI SJ-LDMOS was fabricated and characterized. The tested PSOI SJ-LDMOS exhibits a specific on-state resistance of 1.01mOmegamiddotcm2 while the breakdown voltage is 72.3 V.
Keywords :
power semiconductor devices; semiconductor device breakdown; silicon; silicon-on-insulator; substrates; PSOI SJ-LDMOS; Si; breakdown voltage; bulk silicon substrate; on-state resistance; partial SOI platform; substrate-assisted depletion effect; superjunction power LDMOS; voltage 72.3 V; Doping; Electric resistance; Isolation technology; Microelectronics; Oxidation; Power semiconductor devices; Silicon on insulator technology; Substrates; Testing; Wet etching;
Conference_Titel :
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
Conference_Location :
Jeju Island
Print_ISBN :
1-4244-1095-9
Electronic_ISBN :
1-4244-1096-7
DOI :
10.1109/ISPSD.2007.4294961
