Title :
High Voltage LDMOS Transistors utilizing a Triple Well Architecture
Author :
Puchner, Helmut ; Lee, Sungkwon ; Hinh, Long ; Jang, Jaejune
Author_Institution :
Cypress Semicond., San Jose
Abstract :
We present the integration, device fabrication as well as a reliability analysis of 36 V drain extended CMOS transistors into a 0.35 CMOS baseline technology by utilizing the existing implants and adding 2 additional masking layers. Breakdown voltages >70 V for DENMOS and >60 V for DEPMOS are achieved employing the drain extended device structure. These high breakdown voltages can only be achieved because of careful junction design.
Keywords :
power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device reliability; CMOS transistors; DENMOS; DEPMOS; breakdown voltages; device fabrication; drain extended device structure; high voltage LDMOS transistors; reliability analysis; triple well architecture; voltage 36 V; CMOS process; CMOS technology; Circuits; Costs; Doping; Implants; Low voltage; MOS devices; MOSFETs; Power system reliability;
Conference_Titel :
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
Conference_Location :
Jeju Island
Print_ISBN :
1-4244-1095-9
Electronic_ISBN :
1-4244-1096-7
DOI :
10.1109/ISPSD.2007.4294967
