Title :
Sub-micron Cell Pitch 30 V N-channel UMOSFET with Ultra Low On-resistance
Author :
Kobayashi, Kenya ; Kaneko, Atsushi ; Murase, Yoshimitsu ; Yamamoto, Hideo
Author_Institution :
NEC Electron. Corp., Kawasaki
Abstract :
We developed new sub-micron cell pitch 30 V n-channel UMOSFET with ultra low on-resistance. In the UMOSFET structure, we adopted a layered oxide as interlayer dielectric and equalized the width to the trench gate width to realize the narrow unit cell pitch (<1.0 mum). We optimized layout dimensions for new rectangular cell design and stripe design. As a result, we achieved the lowest specific on-resistance (Rsp) of 4.3 mOmegamm2 at Vgs=10 V and 5.0 mOmegamm2 at Vgs=4.5 V in 30 V class for the fabricated rectangular cell UMOSFET.
Keywords :
power MOSFET; interlayer dielectric; layered oxide; n-channel UMOSFET; rectangular cell design; sub-micron cell pitch; trench gate; ultra low on-resistance; voltage 10 V; voltage 30 V; voltage 4.5 V; Consumer electronics; Design optimization; Dielectrics; Energy management; Low voltage; MOSFETs; National electric code; Personal digital assistants; Power semiconductor devices; Power system management;
Conference_Titel :
Power Semiconductor Devices and IC's, 2007. ISPSD '07. 19th International Symposium on
Conference_Location :
Jeju Island
Print_ISBN :
1-4244-1095-9
Electronic_ISBN :
1-4244-1096-7
DOI :
10.1109/ISPSD.2007.4294968