• DocumentCode
    3313245
  • Title

    Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems

  • Author

    Bak, Stanley ; Yao, Gang ; Pellizzoni, Rodolfo ; Caccamo, Marco

  • Author_Institution
    Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
  • fYear
    2012
  • fDate
    19-22 Aug. 2012
  • Firstpage
    300
  • Lastpage
    309
  • Abstract
    Real-time scheduling of memory-intensive applications is a particularly difficult challenge. On a multi-core system, not only is the CPU scheduling an issue, but equally important is the management of mutual interference among tasks caused by simultaneous access to the shared main memory. To confront this problem, we explore real-time schedulers for task sets which adhere to the Predictable Execution Model (PREM). In each PREM-compliant task, execution is divided into phases which retrieve data from main memory, and phases which perform local computation using previously-cached data. In this work, we perform a simulation-based analysis with the goal of determining which schedulers are generally better at scheduling PREM-compliant task sets. We investigate several memory intensive real-time benchmarks from the EEMBC benchmark suite, in order to drive our task set generation parameters. We elaborate on a PREM-complaint task set simulator which we designed specifically to be able to simulate PREM-compliant tasks. The overall best scheduling policy we found, which we call M-LAX, schedules access to memory in a no preemptive fashion according to a least-laxity-first policy. M-LAX outperforms an EDF-based approach, a previously-analyzed TDMA arbitration scheme, and the unscheduled case where tasks interfere when accessing memory.
  • Keywords
    multiprocessing systems; real-time systems; scheduling; storage management; CPU scheduling; EDF-based approach; EEMBC benchmark suite; M-LAX; PREM-compliant task; cached data; memory-aware scheduling; multicore task sets; predictable execution model; real-time scheduling; real-time systems; scheduling policy; shared main memory; simulation-based analysis; Benchmark testing; Interference; Memory management; Multicore processing; Prefetching; Processor scheduling; Real time systems; M-LAX; PREM; benchmark; eembc; least-laxity first; multicore; predictable execution model; real-time scheduling; scheduling; simulation; simulator; tdma;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded and Real-Time Computing Systems and Applications (RTCSA), 2012 IEEE 18th International Conference on
  • Conference_Location
    Seoul
  • ISSN
    1533-2306
  • Print_ISBN
    978-1-4673-3017-6
  • Electronic_ISBN
    1533-2306
  • Type

    conf

  • DOI
    10.1109/RTCSA.2012.48
  • Filename
    6300162