Design of efficient high throughput pipelined parallel turbo decoder using QPP interleaver

This paper introduces a novel energy efficient architecture for a turbo decoder using quadratic permutation polynomial (QPP) interleaver The Add Compare Select Offset (ACSO) unit of the maximum a posteriori probability (MAP) decoder, has been pipelined to a depth of four to reduce the critical path delay and increase the operating clock frequency and throughput as a consequence. The present turbo decoder architecture also benefits from a contention-free quadratic permutation polynomial (QPP) based interleaver, the complexity of which has been considerably reduced by judicious memory partitioning. Typically, as demonstrated in the present work, 32 MAP decoder core can achieve a data rate of 1.138 Gbps at a maximum clock frequency of 486 MHz when implemented in a 90 nm CMOS process.