Design of a high speed low power linear convolution circuit using McCMOS technique

This paper proposes an efficient design technique of high performance linear convolution of two finite length sequences using Multiple Channel CMOS technique. McCMOS technique uses non-minimum length transistors which offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched capacitance. This paper approaches the linear convolution technique of two finite length sequences as the conventional multiplication procedure A TG array based novel architecture has been proposed for the implementation of the partial products of the multiplication of two input sequences which gives enormously better performance in terms of the power and speed compared to the conventional design. Thorough simulations of the proposed architecture of linear convolution show that the PDP is reduced approximately 77-97% than the conventional linear convolution design. The proposed technique will be very useful in different applications of time and space domains in digital image and signal processing where power and delay are the main area of concerns.