• DocumentCode
    3313497
  • Title

    Laser processes for defect correction in large area VLSI systems

  • Author

    Chapman, G.H.

  • Author_Institution
    Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
  • fYear
    1994
  • fDate
    17-19 Oct 1994
  • Firstpage
    106
  • Lastpage
    114
  • Abstract
    The post fabrication laser processing techniques of cutting lines and forming connections is effective in removing defects and enhancing fault tolerance in large area VLSI circuits. Successful applications require designs which include redundant sections for substitution and defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requires careful attention to the physical aspects of the system including location of the defect avoidance sites and testing considerations. The resulting gains range from significant increases in smaller chip yields to significant expansion of useable circuit area in the large area/wafer scale region with circuit sizes greater than 25 sq. cm
  • Keywords
    wafer-scale integration; area cost; chip yields; circuit size; connections; defect avoidance points; defect correction; error correction time; fault tolerance; large area VLSI circuits; line cutting; post fabrication laser processing; redundancy; substitution; testing; wafer scale region; Circuits; Fault tolerance; Laser beam cutting; Laser theory; Optical arrays; Optical device fabrication; Signal processing; Surface emitting lasers; Transducers; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1550-5774
  • Print_ISBN
    0-8186-6307-3
  • Type

    conf

  • DOI
    10.1109/DFTVS.1994.630020
  • Filename
    630020