Design of cover circuits for monitoring the output of a MISA

Author

Bogue, T. ; Jürgensen, H. ; Gössel, M.

Author_Institution

Dept. of Comput. Sci., Univ. of Western Ontario, London, Ont., Canada

fYear

1994

fDate

17-19 Oct 1994

Firstpage

124

Lastpage

132

Abstract

In this paper, an improved BIST structure is investigated. The output of the MISA is monitored by an error detection circuit during the application of the test sequence. The error detection circuit has to detect only those faults which are aliased by the MISA. By use of this method, no erroneous output sequence of the circuit under test can go undetected. It is demonstrated how the error detection circuit can be realized by two simple cover circuits. Simulation experiments indicate that the hardware overhead for the cover circuits is less than 2% of the circuit under test. It is also demonstrated that in concrete designs the probability of an arbitrary fault-not necessarily in the fault model considered-remaining undetected is significantly smaller than with conventional BIST structure

Keywords

logic analysers; BIST; MISA; aliasing; circuit under test; cover circuits; design; error detection circuit; fault detection; hardware overhead; output monitoring; simulation; Built-in self-test; Circuit faults; Circuit testing; Computerized monitoring; Electrical fault detection; Error correction codes; Fault detection; Hardware; Proposals; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630022

Filename

630022