DocumentCode :
3313623
Title :
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study
Author :
Renovell, M. ; Portal, J.M. ; Figueras, J. ; Zorian, Y.
Author_Institution :
LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear :
1999
fDate :
25-28 May 1999
Firstpage :
146
Lastpage :
151
Abstract :
This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach concerns the XILINX4000 family. On this example of FPGA, a classical test technique consists in first generating test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m/spl times/m array of logic cells. In this classical technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.
Keywords :
SRAM chips; built-in self test; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; LUTs; SRAM-based FPGA; XILINX4000 family; cell array; logic cells; logic modules; multiplexers network; number of test configurations; test configuration minimization; Circuit testing; Computer aided software engineering; Field programmable gate arrays; Identity-based encryption; Logic arrays; Logic testing; Minimization; Portals; Programmable logic arrays; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Test Workshop 1999. Proceedings
Conference_Location :
Constance, Germany
Print_ISBN :
0-7695-0390-X
Type :
conf
DOI :
10.1109/ETW.1999.804520
Filename :
804520
Link To Document :
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