Design of low noise Amplifier using 90nm gate underlap SOI MOSFET for millimeter wave applications

This paper presents the significance of optimization of gate-source/drain extension region engineering (also known as under lap design) in 90nm Silicon-on-Insulator (SOI) MOSFET to improve the performance of a low noise Amplifier (LNA) for millimeter wave (mm-w) applications. A small signal model of underlap SOI MOSFET (with an optimized value of spacer- to- straggle ratio (s/σ) = 3.2 and doping gradient d 5nm/decade) has been developed and implemented in circuit simulator. Based on new Figure - of- Merit (FoM) involving voltage gain A_V, unity gain frequency f_T, forward gain S₂₁, noise figure NF and dc power consumption P_DC, the paper describes the significance of nano-scale SOI underlap design as compared to conventional (non underlap) design. The LNA designed using underlap exhibits nearly 10 dB gain, 4.1 dB NF and 13 mW power consumption in the frequency range from 15-20 GHz, which is suitable for M-Sequence ultra wideband Radar used in automotive vehicle.