Fault tolerant design using error correcting code for multilayer neural networks

Author

Ito, Hideo ; Yagi, Takeshi

Author_Institution

Dept. of Inf. & Comput. Sci., Chiba Univ., Japan

fYear

1994

fDate

17-19 Oct 1994

Firstpage

177

Lastpage

184

Abstract

A new fault tolerant multilayer neural network (NN) which can correct an error caused by a fault in the output layer neuron is proposed. The principle of the design is that an error correcting code is used for the output space of NN, and NN learns this code in the training phase. Simulation experiments for some examples in relatively small pattern recognition models are examined. As a result, it can be concluded that SEC-DED codes together with some training method are sufficient for the examples, and the proposed design can be adapted effectively to practical applications

Keywords

fault tolerant computing; SEC-DED codes; double error detection; error correcting code; fault tolerant design; multilayer neural networks; output layer neuron; output space; pattern recognition models; single error correction; training phase; Circuit faults; Error correction; Error correction codes; Fault tolerance; Hardware; Multi-layer neural network; Neural networks; Neurons; Nonhomogeneous media; Pattern recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Conference_Location

Montreal, Que.

ISSN

1550-5774

Print_ISBN

0-8186-6307-3

Type

conf

DOI

10.1109/DFTVS.1994.630028

Filename

630028