FPGA Implementaton of Strongly Parallel Histogram Equalization

Highly parallel architecture for local histogram equalisation is studied. Three different kinds of approaches to the parallel architecture are regarded in this paper. (1) Module-level -which focuses on processing as many data as possible within a single module. (2) 1D -Several modules conducting simultaneously histogram equalization on partially overlapping (either horizontally or vertically) frames. (3) 2D -utilizes the same approach as 1D but in two dimensions. Beside above-mentioned solutions, differential processing of overlapping frames was also considered. At the end of this paper the optimal proportion of the above mention solutions are studied and implementation results given.