DocumentCode
3314012
Title
Reconfiguration in 3D meshes
Author
Chandra, Anuj ; Melhem, Rami
Author_Institution
Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
fYear
1994
fDate
17-19 Oct 1994
Firstpage
194
Lastpage
202
Abstract
The 1½ track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. It is also shown that switch reconfiguration after faults is local in the sense that the state of each switch is uniquely determined by the state of the processors connected to it
Keywords
reconfigurable architectures; 1 1/2 track model; 3D mesh architectures; compensation paths; fault tolerant processor arrays; switch reconfiguration; Computer science; Fault tolerance; Image processing; Labeling; Magnetic resonance; Nearest neighbor searches; Parallel processing; Switches; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location
Montreal, Que.
ISSN
1550-5774
Print_ISBN
0-8186-6307-3
Type
conf
DOI
10.1109/DFTVS.1994.630030
Filename
630030
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