Efficient residue checker using new binary modular adder tree structure for error detection of arithmetic

An error residue checker for MAC circuit is proposed. By introducing SD number system into error detection arithmetic, an efficient SD residue checker can be implemented. In this paper, by introducing two kinds of modulo m(m^p ± 1) adders, an efficient modulo m binary adder tree is proposed which is used to implement modulo m multiplier(MSDM) and binary-to-residue converter based on SD number arithmetic. By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.