Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation

Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.