DocumentCode
3314217
Title
Built in Defect Prognosis for Embedded Memories
Author
Dubey, Prashant ; Garg, Akhil ; Bhaskarani, Sravan Kumar
Author_Institution
STMicroelectron. India Pvt Ltd., Noida
fYear
2007
fDate
11-13 April 2007
Firstpage
1
Lastpage
6
Abstract
With the shrinking technology and increasing statistical defects, multiple design respins are required based on yield learning. Hence, a solution is required to efficiently diagnose the failure types of memory during production in the shortest time frame possible. This paper introduces a novel method of fault classification through image based prognosis of predefined fail signature dictionary. In contrary to the existing bitmap diagnosis methodologies, this method predicts the compressed failure map without generating and transferring complete bitmap to the tester. The proposed methodology supports testing through a very low cost ATE. This architecture is partitioned to achieve sharing among various memories and at-speed testing.
Keywords
fault diagnosis; image processing; integrated circuit design; integrated circuit testing; integrated memory circuits; at-speed testing; bitmap; defect prognosis; design respins; embedded memories; failure diagnosis; fault classification; image based prognosis; memory testing; predefined fail signature dictionary; shrinking technology; statistical defects; yield learning; Built-in self-test; Circuit faults; Circuit testing; Clocks; Condition monitoring; Costs; Debugging; Production; Routing; Test pattern generators; Bitmap; Diagnostics; Memory test; Yield learning;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
Conference_Location
Krakow
Print_ISBN
1-4244-1162-9
Electronic_ISBN
1-4244-1162-9
Type
conf
DOI
10.1109/DDECS.2007.4295275
Filename
4295275
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