Title :
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
Author :
Tung, Chiou-Kou ; Hung, Yu-Cherng ; Shieh, Shao-Hui ; Huang, Guo-Shing
Author_Institution :
Nat. Chinyi Univ. of Technol., Taichung
Abstract :
In this paper, a low-power high-speed CMOS full adder core is proposed for embedded system. Based on a new three-input exclusive OR (3-XOR) design, the new hybrid full adder is composed of pass-transistor logic and static CMOS logic. The main design objectives for the full adder core are providing not only low power and high speed but also with driving capability. Using TSMC CMOS 0.35-mum technology, the characteristics of the experimental circuit compared with prior literature show that the new adder improves 1.8% to 35.6% in power consumption, 11.7% to 41.2% in time delay of Co, and 13.7% to 91.4% in power-delay product of Co. The circuit is proven to have the minimum power consumption and the fastest response of carry out signal among the adders selected for comparison. Due to the low-power and high-speed properties, both the new exclusive OR circuit and the new full adder can be efficiently integrated in a system-on-a-chip (SoC) or an embedded system.
Keywords :
CMOS logic circuits; adders; embedded systems; logic gates; power consumption; system-on-chip; 3-XOR design; CMOS technology; SoC; carry out signal; embedded system; exclusive OR circuit; high-speed CMOS full adder core; hybrid CMOS full adder; pass-transistor logic; power consumption; power-delay product; size 0.35 mum; static CMOS logic; system-on-a-chip; three-input exclusive OR design; time delay; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Delay effects; Embedded system; Energy consumption; Logic design; SPICE; System-on-a-chip; CMOS; XOR; full adder; pass transistor logic;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE
Conference_Location :
Krakow
Print_ISBN :
1-4244-1162-9
Electronic_ISBN :
1-4244-1162-9
DOI :
10.1109/DDECS.2007.4295280
