Title :
A yield study of VLSI adders
Author :
Chen, Zhan ; Koren, Israel
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17%
Keywords :
adders; 64 bit; VLSI adders; carry-lookahead adder; carry-skip adder; hybrid adder; layout modification; yield study; Adders; Circuits; Conferences; Contracts; Delay; Floating-point arithmetic; Libraries; Process design; Very large scale integration; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-8186-6307-3
DOI :
10.1109/DFTVS.1994.630035
