Title :
Using Fourier analyses to enhance IC testability
Author_Institution :
Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
Abstract :
In this paper, we explore the potential of FFTs in digital IC tests. The effects of three parasite contact types are investigated. Results show that unappropriate logical values on output voltages are easily detected and that FFTs on supply current can make detectable undesired contacts causing additional delays. Application of the method to technologies with non small quiescent currents and to large ICs is also discussed
Keywords :
digital integrated circuits; FFTs; Fourier analyses; IC testability enhancement; digital IC tests; large ICs; parasite contact types; Circuit faults; Circuit testing; Current supplies; Digital integrated circuits; Fault detection; Flexible printed circuits; Frequency estimation; Integrated circuit testing; Logic testing; Voltage;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-8186-6307-3
DOI :
10.1109/DFTVS.1994.630041
