Multi-layer interconnect yield model for mega bit BiCMOS SRAMs

Multi-layer interconnect yield model for mega bit BiCMOS SRAM utilizes the information from the multi-layer interconnect structure and details of the SRAM chip interconnect layout. The multi-layer interconnect yield accurate information concerning the defect size distribution which is a function of the interconnect process technology employed in the SRAM chip. The model is based on the interconnect defect density and multi-layer interconnect area. A case study of 4-Mb BiCMOS SRAM chip yield analysis results are presented